Over the past 30 years, anti-fuse technology has attracted significant attention of many inventors, IC designers and manufacturers. An anti-fuse is a structure alterable to a conductive state, or in other words, an electronic device that changes state from not conducting to conducting. Equivalently, the binary states can be either one of high resistance and low resistance in response to electric stress, such as a programming voltage or current. There have been many attempts to develop and apply anti-fuses in the microelectronic industry, where many anti-fuse applications to date can be seen in FGPA devices manufactured by Actel and Quicklogic, and redundancy or option programming used in DRAM devices by Micron.
An anti-fuse memory is one type of one-time programmable (OTP) memory in which the device can be permanently programmed (electrically) with data once. This data is programmed by an end user for a particular application. There are several types of OTP memory cells which can be used. OTP memories provide users with a level flexibility since any data can be programmed.
FIG. 1 is a circuit diagram of a known anti-fuse memory cell, while FIGS. 2 and 3 show the planar and cross-sectional views respectively of the anti-fuse memory cell shown in FIG. 1. The anti-fuse memory cell of FIG. 1 includes a pass, or access transistor 10 for coupling a bitline BL to a bottom plate of anti-fuse device 12. Anti-fuse device 12 is considered a gate dielectric breakdown based anti-fuse device. A wordline WL is coupled to the gate of access transistor 10 to turn it on, and a cell plate voltage Vcp is coupled to the top plate of anti-fuse device 12 for programming anti-fuse device 12.
It can be seen from FIGS. 2 and 3 that the layout of access transistor 10 and anti-fuse device 12 is very straight-forward and simple. The gate 14 of access transistor 10 and the top plate 16 of anti-fuse device 12 are constructed with the same layer of polysilicon, which extend across active area 18. In the active area 18 underneath each polysilicon layer, is formed a thin gate oxide 20, also known as a gate dielectric, for electrically isolating the polysilicon from the active area underneath. On either side of gate 14 are diffusion regions 22 and 24, where diffusion region 24 is coupled to a bitline. Although not shown, those of skill in the art will understand that standard CMOS processing, such as sidewall spacer formation, lightly doped diffusions (LDD) and diffusion and gate silicidation, can be applied. While the classical single transistor and capacitor cell configuration is widely used, a transistor-only anti-fuse cell is further desirable due to the semiconductor array area savings that can be obtained for high-density applications. Such transistor-only anti-fuses should be reliable while simple to manufacture with a low cost CMOS process.
Because of its low manufacturing cost, anti-fuse memory can be utilized in all one-time programmable applications, from low cost RF-ID tag applications to automotive and security applications. RF-ID tagging applications are gaining more acceptance in the industry, particularly in sales, security, transport, logistics, and military applications for example. The simplicity and full CMOS compatibility anti-fuse memory allows for application of the RF-ID tag concept to integrated circuit manufacturing and testing processes. Therefore, IC manufacturing productivity can be increased by utilizing anti-fuse memory in combination with an RF communication interface on every wafer and/or every die on the wafer allowing for contact-less programming and reading chip specific or wafer specific information during IC manufacturing and packaging, as well as during printed circuit board assembly.
A significant advantage of OTP memory is that the end user, and not the OTP memory manufacturer, has the ability to program the data for a particular application. Therefore cost savings through economies of scale for the manufacturer are realized, while the end user can program any data to the OTP memory. This may be important for some end users, since they may be programming codes or other data that should not be released to others.
In known OTP memory such as the prior art anti-fuse memory cell of FIGS. 1 to 3, one bit of data is stored in one memory cell, and the one memory cell is accessed during a read operation to read out the bit of data stored therein. This is referred to as a single-ended read mode. Storage of the data in anti-fuse memory cells is done through programming, which as previously mentioned is typically done by the end-user. The successful programming of an anti-fuse memory cell depends on parameters such as programming voltage, temperature, and other conditions, which are ideally held at an optimum level. Unfortunately, the end user typically does not have control over such parameters. Hence there is the probability that data may not be programmed to the cells, resulting in failure to program the data. In such a situation, the OTP memory has failed and the anti-fuse memory device is discarded with a renewed attempt to program the data to a new device. In a more problematic scenario, the data may not be properly programmed to the cells because the cell is “weak” or “slow”, meaning that a cell thought to have been programmed with one logic state could be read out to have the opposite logic state. This can cause malfunction of the system relying on the stored data.
Even before delivery to end users, the manufacturer of the memory may encounter defects that render the memory device useless because too many cells cannot be used. This will reduce manufacturing yield, and increase costs. Therefore, there is a need to improve the reliability of anti-fuse memories.